When packets are received, they are typically placed in queues where they may be scheduled for later transmission. Scheduling algorithms, such as weighted fair queuing (“WFQ”) and deficit round robin (“DRR”), may be used to satisfy sophisticated QoS (quality of service) requirements in certain applications and/or equipment where thousands of queues may be supported at extremely high data rates. One example of this is broad-band access using service provider edge equipment. In such scheduling algorithms, the length of the queued packets is a required input to determine which packets to schedule next for transmission. However, since a large number of packet queues is usually required, typical processor architectures implement packet queues in external memory (e.g., a memory external to a network processor). For some applications, packet retrieval may be expensive in terms of read latency and consumed bandwidth.